AWARD
®
BIOS Setup
3-13
DRAM Clock/Drive Control
Press <Enter> to enter the sub-menu, and you will see a sub-menu screen
similar to the following:
Advanced Chipset Features
↑↓→←:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
DRAM Clock/Drive Control Press Enter
AGP & P2P Bridge Control Press Enter
CPU & PCI Bus Control Press Enter
Memory Hole Disabled
System BIOS Cacheable Disabled
Memory Parity/ECC Check Disabled
CMOS Setup Utility - Copyright (C) 1984-2001 Award Software
Advanced Chipset Features
Item Help
Menu Level 8
8
8
8
Current FSB Frequency 100MHz
Current DRAM Frequency 100MHz
DRAM Clock By SPD
DRAM Timing By SPD
DRAM CAS Latency 2.5
Bank Interleave Disabled
DRAM Clock/Drive Control
Item Help
Menu Level 88
x
x
Note: Change these settings only if you are familiar with the chipset.
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