MSI H67MA-E35 User Manual Page 38

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En-28
MS-7680 Mainboard
English
MS-7680 Mainboard
English
Adjusted DRAM Frequency
It shows the adjusted DRAM frequency. Read-only.
DRAM Timing Mode
Select whether DRAM timing is controlled by the SPD (Serial Presence Detect) EE-
PROM on the DRAM module. Setting to [Auto] enables DRAM timings and the following
“Advanced DRAM Conguration” sub-menu to be determined by BIOS based on the
congurations on the SPD. Selecting [Link] or [Unlink] allows users to congure the
DRAM timings and the following related “Advanced DRAM Conguration” sub-menu
manually.
Advanced DRAM Conguration
Press <Enter> to enter the sub-menu.
Command Rate
This setting controls the DRAM command rate.
tCL
This controls the CAS latency, which determines the timing delay (in clock cycles)
before SDRAM starts a read command after receiving it.
tRCD
When DRAM is refreshed, both rows and columns are addressed separately. This
setup item allows you to determine the timing of the transition from RAS (row ad-
dress strobe) to CAS (column address strobe). The less the clock cycles, the faster
the DRAM performance.
tRP
This setting controls the number of cycles for Row Address Strobe (RAS) to be
allowed to precharge. If insucient time is allowed for the RAS to accumulate its
charge before DRAM refresh, refreshing may be incomplete and DRAM may fail
to retain data. This item applies only when synchronous DRAM is installed in the
system.
tRAS
This setting determines the time RAS takes to read from and write to memory cell.
tRFC
This setting determines the time RFC takes to read from and write to a memory
cell.
tWR
Minimum time interval between end of write data burst and the start of a precharge
command. Allows sense ampliers to restore data to cells.
tWTR
Minimum time interval between the end of write data burst and the start of a col-
umn-read command. It allows I/O gating to overdrive sense ampliers before read
command starts.
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