MSI H6M-P23 (B3) Specifications Page 103
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PCI I/O Space and Memory Space Register Description 4-35
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
Reserved [31:4]
This field is reserved.
Write I/O Key [3:0]
To enable write access to the Diagnostic Read/Write Data,
Diagnostic Read/Write Address, and Host Diagnostic reg-
ister, perform five data-specific writes to the Write I/O Key.
Writing an incorrect value to the Write I/O Key invalidates
the key sequence and the host must rewrite the entire
sequence. The Write I/O Key sequence is: 0x00FF,
0x0004, 0x000B, 0x0002, 0x0007, and 0x000D. To disable
write access to the Diagnostic Read/Write Data, Diagnos-
tic Read/Write Address, and Host Diagnostic registers,
perform a write of any value, except the Write I/O Key
sequence, to the Write Sequence register. The Diagnostic
Write Enable bit, bit 7 in the Host Diagnostic register, indi-
cates the write access status.
Register: 0x08
Host Diagnostic
Read/Write
The Host Diagnostic register contains diagnostic controls and status
information. This register can only be written when bit 7 of this register
is set. This bit is set by writing the correct key sequence to the Write
Sequence register.
Reserved [31:11]
This field is reserved.
Clear Flash Bad Signature 10
Writing a one (1) to this bit clears the Flash Bad Signature
setting within the LSISAS1064. This bit is self-clearing.
Prevent IOC Boot 9
Setting this bit prevents the IOP from rebooting after a
reset.
Reserved 8
This field is reserved.
31 24 23 16 15 8 7 0
Host Diagnostic
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0001000 X0
- LSISAS1064 PCI-X 1
- SCSI/SATA Controller 1
- TECHNICAL 1
- Contents 7
- 5.4 Pinout 5-12 9
- 5.5 Package Drawings 5-20 9
- Appendix A Register Summary 9
- Contents xi 11
- Contents xiii 13
- Chapter 1 15
- Introduction 15
- 1-2 Introduction 16
- Example Application 17
- 1.2 Benefits of SAS 18
- 1.4 Benefits of PCI-X 20
- 1.5 Benefits of GigaBlaze 21
- Transceivers 21
- 1.6.2 SATA Features 22
- 1.6.3 PCI Performance 22
- 1.6.4 Integration 23
- 1.6.5 Usability 24
- 1.6.6 Flexibility 24
- 1.6.7 Reliability 24
- 1.6.8 Testability 25
- 1-12 Introduction 26
- Chapter 2 27
- Functional Description 27
- 2.1 Block Diagram Description 28
- Block Diagram Description 2-3 29
- 2-4 Functional Description 30
- Block Diagram Description 2-5 31
- 2.1.2 Quad Port 32
- 2.1.3 Context RAM 33
- 2-8 Functional Description 34
- 2.3.1 PCI Addressing 35
- 2-12 Functional Description 38
- 2-14 Functional Description 40
- 2.3.3 PCI Arbitration 41
- 2.3.4 PCI Cache Mode 41
- 2.3.5 PCI Interrupts 42
- 2.3.6 Power Management 42
- 2-18 Functional Description 44
- 2.5 External Memory Interface 45
- 2.5.2 Flash ROM Controller 46
- Bytes [3:0] 0xEA 47
- XX XX XX 47
- 2.5.3 NVSRAM Controller 48
- 2.6 Zero Channel RAID 49
- 2-24 Functional Description 50
- 2.8 Multi-ICE Test Interface 51
- 2-26 Functional Description 52
- Chapter 3 53
- Signal Description 53
- • SAS Interface 54
- • Memory Interface 54
- • Communication Interface 54
- • JTAG and Test Interface 54
- Signal Organization 3-3 55
- 3.2 PCI Signals 56
- 3.2.4 PCI Arbitration Signals 57
- 3.3 PCI-Related Signals 58
- 3.4 Compact PCI Signals 59
- 3.5 SAS Signals 59
- 3.6 Memory Interface Signals 60
- 3.7 Communication Signals 61
- 3.9 JTAG and Test Signals 63
- 3.10 Power Signals 64
- Chapter 4 69
- PCI Host Register 69
- Description 69
- 31 16 15 0 Offset Page 70
- Register: 0x00–0x01 71
- Register: 0x02–0x03 71
- Register: 0x04–0x05 71
- Register: 0x06–0x07 73
- 0b00 Fast 74
- 0b01 Medium 74
- 0b10 Slow 74
- 0b11 Reserved 74
- Register: 0x09–0x0B 75
- Register: 0x0D 76
- Register: 0x0E 77
- Register: 0x0F 77
- Register: 0x10–0x13 77
- Register: 0x14–0x17 78
- Register: 0x18–0x1B 78
- Register: 0x1C–0x1F 79
- Register: 0x20–0x23 79
- Register: 0x24–0x27 80
- Register: 0x28–0x2B 80
- Register: 0x2C–0x2D 80
- Register: 0x2E–0x2F 81
- Register: 0x30–0x33 81
- Register: 0x35–0x37 83
- Register: 0x38–0x3B 83
- Register: 0x3C 83
- Register: 0x3D 84
- Register: 0x3E 84
- Register: 0x3F 84
- Register: 0xXX 85
- Register: 0x00 102
- Register: 0x04 102
- Register: 0x08 103
- Register: 0x0C 105
- Register: 0x10 105
- Register: 0x30 106
- Register: 0x14 106
- Register: 0x34 107
- Register: 0x40 108
- Register: 0x44 109
- Register: 0x48 109
- Chapter 5 111
- Specifications 111
- TMUX_SPARE[7:0] 117
- Table 5.23 Capacitance 117
- 5.2 AC Characteristics 118
- Figure 5.4 Flash Write 120
- Figure 5.5 Flash Read 121
- Figure 5.6 NV Read 121
- 5.4 Pinout 122
- Pinout 5-13 123
- SignalPinSignalPin 123
- SignalPin SignalPin 123
- 5-14 Specifications 124
- Pinout 5-15 125
- 5-16 Specifications 126
- Pinout 5-17 127
- 5-18 Specifications 128
- Pinout 5-19 129
- 5.5 Package Drawings 130
- Package Drawings 5-21 131
- 5-22 Specifications 132
- Package Drawings 5-23 133
- 5-24 Specifications 134
- Appendix A 135
- Register Summary 135
- – Read Only 4-26 137
- – Read Only 4-27 137
- Read/Write Page 137
- Numerics 139
- register 4-27 143
- register 4-26 143
- IX-12 Index 150
- Customer Feedback 151
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