MSI H6M-P23 (B3) Specifications download pdf (Page 143)

Index IX-5

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memory [0] low 4-5, 4-10

memory [1] high 4-5, 4-11

memory [1] low 4-5, 4-11

memory read 4-30

memory requirements 2-19

memory space 2-10, 4-32

message passing technology 2-1

message queues 2-7, 2-8

message signaled interrupts 2-16

MFA

high priority request 4-41

reply 4-41

minimum grant register 4-16

MODE[5:0] 3-10, 3-16, 5-4

MOE[1:0]/ 3-8, 5-6

MSI 2-16, 4-39

capability ID register 4-20

enable bit 4-22

mask bits 4-24

message address 4-22

message data 4-23

message upper address register 4-23

multiple message 4-22

next pointer register 4-20

pending bits 4-24

MSI mask bits register 4-24

MSI message address register 4-22

MSI message control register 4-21

MSI message data register 4-23

MSI message upper address register 4-23

MSI pending bits register 4-24

MSI-X 2-16, 4-39

capability ID register 4-24

next pointer register 4-25

PBA offset 4-27

table offset 4-26

MSI-X enable 3-14, 3-15

MSI-X message control register 4-25

MSI-X PBA offset register 4-27

MSI-X table offset register 4-26

multi-ICE 2-25

multiple cache line transfers 2-15

multiple message capable 4-22

multiple message enable 4-21

MWE[1:0]/ 3-8, 5-6

N

narrow port 2-17

NC 3-1, 3-13

new capabilities bit 4-7

no connect 3-1

NVSRAM 2-22

NVSRAM or SRAM select 3-14

NVSRAM/SRAM installed 3-14

NVSRAM_CS/ 3-8, 5-6

O

operating conditions 5-2

operating free air temperature 5-2

P

package drawing 5-18, 5-19, 5-20

PAR 3-4, 5-3

PAR64 3-4, 5-3

parity error 4-6

PBA offset 4-27

PC2001 system design guide 2-16

PCI 2-7, 2-8

33 MHz 5-8

64-bit 3-14, 3-15

66 MHz 3-14, 3-15, 5-8

66 MHz capable bit 4-6

address/data bus 3-13, 4-31

addressing 2-9

alias to memory read block command 2-12,

2-14

alias to memory write block command 2-12

arbitration 2-15

arbitration signals 3-5

benefits 1-6

bus commands 2-10

cache line size register 2-14

cache mode 2-15

CLK 5-8

command 2-10

configuration read 2-9, 2-10, 2-12

configuration write 2-9, 2-10, 2-13

dual address cycle 2-14

dual address cycles 2-8

I/O read 2-10, 2-11

I/O write 2-10

I/O write command 2-11

interrupt acknowledge 2-10, 2-11

memory read 2-10

memory read block 2-11, 2-12, 2-14

1 2 ... 138 139 140 141 142 143 144 145 146 147 148 ... 151 152

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