5-12 Specifications
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
Figure 5.7 NV Write
5.4 Pinout
Table 5.31 provides the signal listing by signal name. Table 5.32 provides
the BGA pin listing. Figure 5.8 provides a BGA diagram.
Table 5.30 NVRAM Write Timing Parameters
Symbol Parameter Min Max Unit
t
4
NVRAM Address Setup to NVRAM_CS/ (Write) 10 – ns
t
5
NVRAM Address Setup to BWE/ (Write Enables) 10 – ns
t
6
NVRAM_CS/ Width (Write) 15 400 ns
t
7
NVRAM Write Recover 0 40 ns
– NVRAM Write Cycle Time 25 460 ns
MA
MD[31:24]
NVRAMCS/
BWE2/
MOE/
A(00) A(01) A(10) A(11) A=4(00)
D3
D2
D1D0
t
4
t
7
t
5
t
5
t
4
t
6
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