MSI H6M-P23 (B3) Specifications Page 40
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2-14 Functional Description
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
transactions when operating in the PCI-X mode. A split transaction
consists of at least two separate bus transactions: a split request, which
the requester initiates, and one or more split completion commands,
which the completer initiates. Revision 2.0 of the PCI-X addendum
permits split transaction completion for the Memory Read Block, Alias to
Memory Read Block, Memory Read Dword, Interrupt Acknowledge,
I/O Read, I/O Write, Configuration Read, and Configuration Write
commands. When operating in the PCI-X mode, the LSISAS1064
supports the Split Completion command for all of these commands
except the Interrupt Acknowledge command, which the LSISAS1064
neither responds to nor generates.
2.3.2.14 Dual Address Cycles (DAC) Command
The LSISAS1064 performs Dual Address Cycles (DAC), per the PCI
Local Bus Specification, Version 3.0. The LSISAS1064 supports this
command when operating in either the PCI or PCI-X bus mode.
2.3.2.15 Memory Read Line Command
This command is identical to the Memory Read command except it
additionally indicates that the master intends to fetch a complete cache
line. The LSISAS1064 supports this command when operating in the PCI
mode.
2.3.2.16 Memory Read Block Command
The LSISAS1064 uses this command to read from memory. The
LSISAS1064 supports this command when operating in the PCI-X mode.
2.3.2.17 Memory Write and Invalidate Command
The Memory Write and Invalidate command is identical to the Memory
Write command, except it additionally guarantees a minimum transfer of
one complete cache line. The master uses this command when it intends
to write all bytes within the addressed cache line in a single PCI
transaction unless interrupted by the target. This command requires
implementation of the PCI Cache Line Size register. The LSISAS1064
determines when to issue a Write and Invalidate command instead of a
Memory Write command and supports this command when operating in
the PCI bus mode.
- LSISAS1064 PCI-X 1
- SCSI/SATA Controller 1
- TECHNICAL 1
- Contents 7
- 5.4 Pinout 5-12 9
- 5.5 Package Drawings 5-20 9
- Appendix A Register Summary 9
- Contents xi 11
- Contents xiii 13
- Chapter 1 15
- Introduction 15
- 1-2 Introduction 16
- Example Application 17
- 1.2 Benefits of SAS 18
- 1.4 Benefits of PCI-X 20
- 1.5 Benefits of GigaBlaze 21
- Transceivers 21
- 1.6.2 SATA Features 22
- 1.6.3 PCI Performance 22
- 1.6.4 Integration 23
- 1.6.5 Usability 24
- 1.6.6 Flexibility 24
- 1.6.7 Reliability 24
- 1.6.8 Testability 25
- 1-12 Introduction 26
- Chapter 2 27
- Functional Description 27
- 2.1 Block Diagram Description 28
- Block Diagram Description 2-3 29
- 2-4 Functional Description 30
- Block Diagram Description 2-5 31
- 2.1.2 Quad Port 32
- 2.1.3 Context RAM 33
- 2-8 Functional Description 34
- 2.3.1 PCI Addressing 35
- 2-12 Functional Description 38
- 2-14 Functional Description 40
- 2.3.3 PCI Arbitration 41
- 2.3.4 PCI Cache Mode 41
- 2.3.5 PCI Interrupts 42
- 2.3.6 Power Management 42
- 2-18 Functional Description 44
- 2.5 External Memory Interface 45
- 2.5.2 Flash ROM Controller 46
- Bytes [3:0] 0xEA 47
- XX XX XX 47
- 2.5.3 NVSRAM Controller 48
- 2.6 Zero Channel RAID 49
- 2-24 Functional Description 50
- 2.8 Multi-ICE Test Interface 51
- 2-26 Functional Description 52
- Chapter 3 53
- Signal Description 53
- • SAS Interface 54
- • Memory Interface 54
- • Communication Interface 54
- • JTAG and Test Interface 54
- Signal Organization 3-3 55
- 3.2 PCI Signals 56
- 3.2.4 PCI Arbitration Signals 57
- 3.3 PCI-Related Signals 58
- 3.4 Compact PCI Signals 59
- 3.5 SAS Signals 59
- 3.6 Memory Interface Signals 60
- 3.7 Communication Signals 61
- 3.9 JTAG and Test Signals 63
- 3.10 Power Signals 64
- Chapter 4 69
- PCI Host Register 69
- Description 69
- 31 16 15 0 Offset Page 70
- Register: 0x00–0x01 71
- Register: 0x02–0x03 71
- Register: 0x04–0x05 71
- Register: 0x06–0x07 73
- 0b00 Fast 74
- 0b01 Medium 74
- 0b10 Slow 74
- 0b11 Reserved 74
- Register: 0x09–0x0B 75
- Register: 0x0D 76
- Register: 0x0E 77
- Register: 0x0F 77
- Register: 0x10–0x13 77
- Register: 0x14–0x17 78
- Register: 0x18–0x1B 78
- Register: 0x1C–0x1F 79
- Register: 0x20–0x23 79
- Register: 0x24–0x27 80
- Register: 0x28–0x2B 80
- Register: 0x2C–0x2D 80
- Register: 0x2E–0x2F 81
- Register: 0x30–0x33 81
- Register: 0x35–0x37 83
- Register: 0x38–0x3B 83
- Register: 0x3C 83
- Register: 0x3D 84
- Register: 0x3E 84
- Register: 0x3F 84
- Register: 0xXX 85
- Register: 0x00 102
- Register: 0x04 102
- Register: 0x08 103
- Register: 0x0C 105
- Register: 0x10 105
- Register: 0x30 106
- Register: 0x14 106
- Register: 0x34 107
- Register: 0x40 108
- Register: 0x44 109
- Register: 0x48 109
- Chapter 5 111
- Specifications 111
- TMUX_SPARE[7:0] 117
- Table 5.23 Capacitance 117
- 5.2 AC Characteristics 118
- Figure 5.4 Flash Write 120
- Figure 5.5 Flash Read 121
- Figure 5.6 NV Read 121
- 5.4 Pinout 122
- Pinout 5-13 123
- SignalPinSignalPin 123
- SignalPin SignalPin 123
- 5-14 Specifications 124
- Pinout 5-15 125
- 5-16 Specifications 126
- Pinout 5-17 127
- 5-18 Specifications 128
- Pinout 5-19 129
- 5.5 Package Drawings 130
- Package Drawings 5-21 131
- 5-22 Specifications 132
- Package Drawings 5-23 133
- 5-24 Specifications 134
- Appendix A 135
- Register Summary 135
- – Read Only 4-26 137
- – Read Only 4-27 137
- Read/Write Page 137
- Numerics 139
- register 4-27 143
- register 4-26 143
- IX-12 Index 150
- Customer Feedback 151
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