Contents xiii
Version 3.1 Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
Tables
2.1 PCI/PCI-X Bus Commands and Encodings 2-10
2.2 Flash ROM Signature Value 2-21
2.3 ARM Multi-ICE Header Pinout 2-25
3.1 PCI System Signals 3-4
3.2 PCI Address and Data Signals 3-4
3.3 PCI Interface Control Signals 3-5
3.4 PCI Arbitration Signals 3-5
3.5 PCI Error Reporting Signals 3-5
3.6 PCI Interrupt Signals 3-6
3.7 PCI-Related Signals 3-6
3.8 CompactPCI Signals 3-7
3.9 SAS Interface Signals 3-7
3.10 Memory Interface Signals 3-8
3.11 UART and I
2
C Signals 3-9
3.12 Configuration and General Purpose Signals 3-10
3.13 Test and JTAG Signals 3-11
3.14 Power and Ground Signals 3-12
3.15 Power-On Sense Pin Definitions 3-14
3.16 Pull-Up and Pull-Down Conditions 3-16
4.1 LSISAS1064 PCI Configuration Space Address Map 4-2
4.2 Multiple Message Enable Field Bit Encoding 4-21
4.3 BIR Field Definitions 4-26
4.4 Maximum Outstanding Split Transactions 4-28
4.5 Maximum Memory Read Count 4-29
4.6 PCI I/O Space Address Map 4-33
4.7 PCI Memory [0] Address Map 4-33
4.8 PCI Memory [1] Address Map 4-33
4.9 Interrupt Signal Routing 4-40
5.1 Absolute Maximum Stress Ratings 5-2
5.2 Operating Conditions 5-2
5.3 GigaBlaze Transmitter Voltage Characteristics –
TX[3:0] 5-2
5.4 GigaBlaze Receiver Voltage Characteristics – RX[3:0] 5-3
5.5 GigaBlaze Transceiver Rise/Fall Characteristics –
TX[3:0], RX[3:0] 5-3
5.6 PCI-X Input Signals – CLK, RST/, GNT/, IDSEL,
ALT_GNT/, CPCI64_EN/ 5-3
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