MSI H6M-P23 (B3) Specifications download pdf (Page 74)

4-6 PCI Host Register Description

Received Target Abort (from Master) 12

A master device sets this bit when a Target Abort

command terminates its transaction.

Signaled Target Abort 11

The target device must set this bit when it terminates a

transaction with a target abort command.

DEVSEL/ Timing [10:9]

These two read only bits encode the timing of DEVSEL/

and indicate the slowest time that a device asserts

DEVSEL/ for any bus command except Conﬁguration

Read and Conﬁguration Write. The LSISAS1064 only

supports medium DEVSEL/ timing. The possible timing

values are:

Data Parity Error Reported 8

This bit is set per the PCI Local Bus Speciﬁcation,

Revision 3.0, and PCI-X Addendum to the PCI Local Bus

Speciﬁcation, Revision 2.0. Refer to bit 0 of the PCI-X

Command register for more information.

Reserved [7:6]

This ﬁeld is reserved.

66 MHz Capable 5

The MAD[13] Power-On Sense pin controls this bit.

Allowing the internal pull-down to pull MAD[13] LOW sets

this bit and indicates to the host system that the

LSISAS1064 PCI function is capable of operating at

66 MHz. Pulling MAD[13] HIGH clears this bit and

indicates to the host system that the LSISAS1064 PCI

function is not conﬁgured to operate at 66 MHz. Refer to

Section 3.11, “Power-On Sense Pins Description,” for

more information.

0b00 Fast

0b01 Medium

0b10 Slow

0b11 Reserved

1 2 ... 69 70 71 72 73 74 75 76 77 78 79 ... 151 152

No comments

MSI H6M-P23 (B3) Specifications Page 74